Passage EVK100

Exascale Connectivity for AI

Passage EVK100 represents a giant leap in photonic interconnect performance. Designed for the extreme demands of scale-up AI networks, it delivers massive bandwidth density and unprecedented energy efficiency.

Aggregate I/O

3.2

Tbps aggregate bandwidth @ 112G PAM4

Efficiency Target

3.4

pJ/bit target link efficiency @ 112G PAM4

Innovation

The Scale-Out Solution

Lightmatter’s second-generation link platform is engineered to meet the bandwidth explosion of exascale AI superpods. By integrating advanced Photonic Integrated Circuits (PIC) with high-performance optical SerDes chiplets in a 2D multi-chip package, Passage EVK100 de-risks the most aggressive roadmaps in the industry.

Aggregate Bandwidth

3.2 Tbps bidirectional aggregate bandwidth

Link Configuration

Dual-mode flexibility (UniDi / BiDi)

Modulation Support

106G PAM4 signaling

Packaging Architecture

2D multi-chip packaging

Laser Stability

Peak Gain Tracker (PGT) stabilization

System Compatibility

OCP-compliant chassis readiness

Architecture

Optimized for High Spectral Density

Passage EVK100 uses a 16-wavelength 112G PAM4 DWDM architecture to maximize bandwidth within a compact optical footprint. The system supports two operating modes: 1.7 Tbps unidirectional (separate Tx/Rx fibers) or 3.4 Tbps bidirectional transmission on a single fiber using advanced circulators.

Designed for scale-up AI networks, the platform leverages high baud rates to maximize link efficiency. Performance estimates assume 5% wall-plug efficiency (WPE) for future Guide laser integration.

Link Architecture

1,600 Gbps per fiber strand enabled by a 16-channel DWDM architecture across the 1310 nm band.

Technical Specifications

Modulation formats
53G NRZ, 106G PAM4
Link architecture
16λ bidirectional DWDM (3.2 Tbps aggregate)
Wavelength grid
200 GHz spacing centered at 1310 nm (O-band)
Throughput modes
1.7 Tbps (UniDi) / 3.4 Tbps (BiDi aggregate)
Fiber count
2 fibers (UniDi) / 1 fiber (BiDi)
Packaging technology
Horizon 2D multi-chip integration
Efficiency target
3.4 pJ/bit @112G PAM4 (Laser 1.6 · TIA 0.49 · Ctrl 0.55 · PIC/Other 0.76)
Pre-FEC BER target
< 1e-5
Chassis form factor
OCP-compliant rack integration

The Future of Exascale

Passage EVK100 is the standard-bearer for AI infrastructure. Contact our engineering team for deep-dive technical reviews and integration roadmaps.