Lightmatter at EETimes Chiplet Pavilion at the Design Automation Conference
Lightmatter will exhibit at the Design Automation Conference (DAC) 2025 within the EETimes Chiplet Pavillion, a key event focused on the role of chiplet technology in advancing high-performance computing (HPC), AI, and efficient data center scaling. This industry forum will explore the chiplet ecosystem and vital new directions like optical chip-to-chip connectivity, providing an ideal platform for Lightmatter. Here, we will showcase our pioneering work in 3D photonic interconnects, integral to developing the next generation of AI infrastructure.
HIGHLIGHTS
Hear from Ritesh Jain, our SVP of Engineering & Operations as he joins Sally Ward-Foxton’s panel discussion on “Enabling New Design Directions.”
Join Eric Yeh, Head of Product Marketing, for his technical presentation, “Unleashing AI Performance: Silicon Photonic Interconnects for the Next Wave of Acceleration.”
Stop by the Lightmatter kiosk at your convenience during the conference to learn more about our innovative solutions. We eagerly anticipate meeting you at DAC!
DETAILS
Lightmatter Kiosk
Date: Monday – Wednesday, June 23rd – 25th, 2025
Time: M/T 10 AM – 6 PM, W 10 AM – 4 PM
Location: Level 2, Exhibit Hall Booth 2308
Panel Discussion: Enabling New Design Directions
Date: Wednesday, June 25th, 2025
Time: 11:10 AM – 12:05 PM PDT
Location: Level 2, Exhibit Hall Booth 2308
Lightmatter Speaker: Ritesh Jain, SVP, Engineering & Operations, Lightmatter
Description: Chiplets are redefining design possibilities, enabling breakthroughs in compute and memory integration, heterogeneous architectures, and solutions beyond the reticle limit. This session will explore the evolving industry landscape, the role of advanced design tools in ensuring high-performance chiplet-based systems, and the benefits and limitations of interconnect standards like UCIe and BoW. Key applications and market drivers will be examined. Finally, we will discuss the potential of optical chip-to-chip communication and its implications for the future of high-speed, efficient computing architectures in AI and beyond.
Technical Presentation: Unleashing AI Performance: Silicon Photonic Interconnects for the Next Wave of Acceleration
Date: Wednesday, June 25th, 2025
Time: 12:35 PM – 12:55 PM PDT
Location: Level 2, Exhibit Hall Booth 2308
Lightmatter Speaker: Eric Yeh, Head of Product Marketing
Description: As AI workloads continue to scale, both training and inference are driving unprecedented demand for bandwidth, efficiency, and performance at the system level. Conventional interconnect technologies are quickly approaching their limits, making way for a new era powered by silicon photonics. In this presentation, Eric will explore how silicon photonic interconnects are poised to unlock the bandwidth required to support the next generation of AI chips, while simultaneously enabling lower power consumption, longer reach, and dramatically improved AI performance. He will highlight recent innovations from Lightmatter and share a forward-looking perspective on how this transformative technology can meet the growing demands of AI infrastructure, delivering higher compute efficiency, lower energy per bit, and reduced total cost of ownership. Silicon photonics is no longer a future promise. It’s becoming the only viable path to scale AI performance efficiently and sustainably.
Register for free with “I Love DAC” pass using code EETIMES by June 9th: https://bit.ly/3ZgpYDQ
Learn more about our solutions:
Passage L200 3D CPO (co-packaged optics)Passage M1000 Superchip (active photonic interposer)